1) Field of the Invention
This invention relates to semiconductor devices and more particularly to an improved structure and method for producing field effect transistor devices.
2) Description of the Prior Art
As integrated logic and memory circuit devices are microminiaturized, individual element are packed more closely and element size is reduced. Microminiaturization increases the speed of operation and reduces the production costs. In order to achieve this, each memory element must occupy less space on the device. Also, to reduce production costs, the process must be easy to reproduce and the device designed to increase manufacturing yields.
In particular, as memory and logic devices are scaled down in size, there is a continuous challenge is to produce buried source and drain regions with smaller line pitches and lower sheet resistance. However, as line pitches decrease, the buried line sheet resistance increases. Moreover, as the line sheet resistance increase, memory and logic circuit performance decrease. These relationships present the process designer with a trade off problem between smaller buried conductive regions and better circuit performance.
Smaller buried conductive regions create other process related problems. Buried conductive lines are designed with higher impurity concentrations to lower the line resistivity. During oxidation processes, the highly doped line areas oxidize at a higher rate than the lower doped surrounding areas. This enhanced oxidation rate is a function of the doping level of the highly doped line areas, but with the usual doping levels, the doped areas oxidize about four times as fast as the undoped areas. This enhanced oxidation creates surface topology steps between the non-doped device areas and the doped line area. The surface topology can cause yield problems in subsequent layers. The topology can cause photolithography depth of field and focusing problems. Another problem caused by the enhanced oxidation is that polysilicon layers have notching problems when applied over uneven topologies. Therefore, the ideal buried conductive region has a small pitch, a low resistivity and an even surface topology after subsequent oxidations.
In conventional processes for forming buried conductive lines a field oxidation 12 is formed on the substrate surface in non-device areas as shown in FIG. 1. For this example, the substrate 10 is P-type and the conductive lines to be formed will be N-type. The opposite impurity types could be used. Also, an opposite impurity well formation could be used to form both conductivity type devices on the same substrate. Next, a gate oxide 14 is formed over the areas between the field oxide regions 12.
At this point, a first ion implantation (not shown) of P-type ions, called a threshold voltage implant, is performed on regions not covered by the field oxide. The threshold voltage implant's purpose is to increase the threshold voltage of the transistor devices. The threshold voltage is the gate-to-source voltage below which the drain-to-source current effectively drops to zero. Next, another ion implantation (not shown) of P-type ions at a higher implant energy, called a anti-punch through implantation, can be performed on the same regions not covered by field oxide. This implant is designed to increase the device punch-through voltage. Punchthrough can occur if very high voltages are applied to the drain. Under these circumstances, the gate had no control over the drain current. The higher the punch-through voltage the wider the device operating voltage range and the better the device.
Subsequently, as shown in FIG. 2, a resist layer 16 is formed having openings 18 in areas which will define the conductive lines. N-type impurity ions are ion implanted through the resist openings 18 to form doped regions 20. The resist is removed and the doped regions are annealed to electrically activate the implanted ions and form the buried conductive regions 20. Next the substrate is oxidized to form a second gate oxide layer 26 as shown in FIG. 3. However, the surface of the buried conductive line region oxidizes at a faster rate than the lower doped surrounding areas as is well known. This enhanced oxidation creates a step topology 24. This step topology 24 can cause the previously mentioned processing problems: photolithography depth of field focus problems and notching problems in the subsequent polysilicon layers.
Lebowitz et. al. U.S. Pat. No. 4,653,177 discloses a method for fabricating and selectively doping isolation trenches in complementary-metal-oxide-semiconductor devices (CMOS). The invention describes two non-lithographic techniques where selective anodic oxidation is used to selectively mask the sidewalls of the trenches. The first technique to anodize the p-type trench isolations regions begins by preferentially etching the p-type regions followed by an oxidation of the etched p-type areas. The second technique to anodize the p-type isolation regions uses a dry anodization process in a plasma environment. These non-lithographic masking techniques are followed by an introduction of a n-type impurity into the unmasked areas. The n-type impurity can be introduced in several ways: ion implantation, n-doped polysilicon layer diffusion, and diffusion for gases or solids.
Yamada et. al. U.S. Pat. No. 5,156,985 discloses a method for making a charge transfer semiconductor device having an oblong trench. The invention describes forming a trench with two layers, a N-type layer and a P-type layer, on the trench sidewalls and bottom. These layers can have different doping levels on the trench sides and bottom. The trench sidewalls are doped using a oblique ion implantation. The trench bottom is doped using a vertical (90 degree) ion implantation.
Hasaka U.S. Pat. No. 5,118,636 teaches a process for forming an isolation trench in previously implanted region. The invention has two basic steps: 1) forming a doped region by ion implantation, and 2) forming a trench in the ion implanted region.
Kimura U.S. Pat. No. 5,114,865 discloses a process to manufacture a solid-state image sensing device having a overflow drain structure. The invention describes the formation of metal-oxide semiconductor (MOS) devices (overflow drain structure and an optoelector transducer) inside trenches. The trenches have three different doped regions, one N-type and two P-type. The doped regions serve as drain and channel and other elements. The trench walls are implanted at oblique angles to form one N-type and one P-type layer. The other P-type region is formed in the substrate before the trench is etched.